The example embodiments relate to scan chain control for testing electronic circuits.
Scan chains are typically included in various electronic circuits for testing manufacturing defects. Such electronic circuits include various integrated circuits, such as system-on-chip (SoC) circuits that generally provide a single integrated circuit with all required circuitry to perform a desired set of functions. A scan chain is generally a set of added circuitry that includes and operates generally in three operations: (i) sequentially scanning a known data sequence of 0 and 1 values into a series-connected set, or “chain”, of circuit flip flops; (ii) applying that test data sequence to logic circuitry connected to outputs from the flip flop chain; and (iii) returning the logic circuitry output to the flip flop chain and scanning out the captured result, so as to compare it with an expected result. If the output matches the expected result, proper circuitry operation is thereby confirmed; conversely, if there is a mismatch, a potential fault may be thereby detected. Typically, scan testing is conducted via automated test equipment (ATE) that is programmed with test patterns, so that numerous different sequences may be loaded and compared against respective expected results. Failure comparisons may identify faults within the circuit, for purposes of evaluating device yield and also prohibiting unreliable devices from being released to the market.
Power consumption during scan chain testing is a factor for consideration. The number of flip flops in a scan chain, the number of modules of the device under test (DUT), and the frequency of the shifting through the chains all contribute to such power consumption. Further, the DUT will have a specified functional power limit for its normal (non-testing) operation. Accordingly, total or peak power consumption during scan testing cannot, or should not, exceed the functional power limit. Some earlier methods seek to limit test power consumption by selectively enabling/disabling different scan chains and/or different portions of the DUT during scan testing. Such methods impose static schedules on the scan shift operation. Additionally, such static techniques are typically fairly conservative, thereby avoiding excessive power consumption, but necessarily reducing scan data bandwidth and increasing the time required to test the DUT. While the test time increase due to slow scan shift frequency may not be significant for one module in the DUT, it would not be insignificant for today's complex SOCs which have several such modules (often in excess of 20). Other methods include additional circuitry to gate, or block, an output of a flip flop in a chain from continuing to the input of the combinational logic, so as to prevent any toggling (change of output state). This approach increases area consumed by the circuit on account of the additional gating circuitry and also imposes timing delays during functional mode. Another approach requires special adherence by each test sequence as part of the automatic test pattern generation (ATPG) process, whereby each test pattern is acceptable only if it does not cause a certain allowable maximum amount of toggling in the chain to be exceeded. This approach can result in excessive numbers of necessary test patterns (and the time expenditure to apply such patterns) or the ATPG tool may not be able to adhere to such conditions.
Accordingly, example embodiments are provided in this document that may improve on certain of the above concepts, as further detailed below.